1. Field of the Invention
The present invention relates to an apparatus and method for driving a plasma display panel (PDP).
2. Discussion of the Related Art
Various types of flat panel displays, including liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs, are being developed. Generally, the PDP has higher resolution, higher emission efficiency, and a wider viewing angle than other flat panel displays. Accordingly, it is regarded as a principle substitute for the conventional cathode ray tube (CRT), especially for large-sized displays greater than forty inches.
The PDP displays characters or images using plasma generated by gas discharge, and it may include hundreds of thousands to millions of pixels arranged in a matrix format, depending upon its size. Plasma display panels are typically divided into direct current (DC) and alternating current (AC) type PDPs according to an applied driving voltage waveform and discharge cell structure.
Since electrodes of the DC PDP are exposed in a discharge space where current flows due to an applied voltage, a resistor is required for current limitation. To the contrary, a dielectric layer covers the electrodes of the AC PDP and limits currents because of naturally forming capacitance components. Further, the dielectric layer protects the electrodes from ion impulses during discharging, which provides the AC PDP with a longer life span than the DC PDP.
Pairs of scan electrodes and sustain electrodes are formed on a first substrate of the AC PDP, and address electrodes are formed crossing them on a second substrate. The sustain electrodes may be formed corresponding to each scan electrode.
A conventional method for driving the AC PDP includes a reset period, an address period, and a sustain period, which are represented by changes of the operation according to time.
In the reset period, a status of each cell is initialized so as to stably perform subsequent address discharging. In the address period, an address voltage is applied to cells that are to be turned on (addressed cells), and wall charges accumulate to the addressed cells. In the sustain period, a discharge for displaying images on the addressed cells is performed.
In a conventional PDP, the sustain and scan electrode driving circuits generate sustain discharge voltage pulses. However, more circuit units may be included in the scan electrode driving circuit because it may also generate reset and scan pulses, in addition to the sustain discharge pulses.
FIG. 1 is a diagram showing a conventional scan electrode driving circuit.
As shown FIG. 1, a conventional scan electrode driving circuit may include a sustain driver 221, including a power recovery circuit, a reset driver 222, including a main path switch, and a scan driver 223, including a scan integrated circuit (IC).
As shown by the arrow in FIG. 1, applying a discharge voltage to the scan electrode (represented by a terminal of the panel capacitor Cp) from the sustain driver 221 forms a current path that passes through the reset driver 222, including the main path switch, and the scan driver 223.
Parasitic inductance (circled in FIG. 1) formed by a pattern on the main discharge path may distort voltage waveforms, which may degrade discharge states. This degradation may worsen as the panel size increases.